Semiconductor Device With Sidewall Spacers Having Minimized Area Contacts

ABSTRACT

Contact openings are formed in a dielectric layer overlying conductive paths where the openings and the paths have essentially the same dimension or width, thus allowing for minimized area contacts. Process buffering regions are formed adjacent the conductive paths to provide additional landing area for the contact openings without exposing the sidewall of the conductive path. In some embodiments the contact openings and methods for forming thereof provide electrical coupling between metal layers of a multilevel metal structure or for electrically coupling polysilicon layers and metal layers. In some embodiments the contact opening and methods for forming thereof provide for direct contact to a gate electrode.

BACKGROUND

[0001] 1. Field of the Invention

[0002] This invention relates to semiconductor integrated circuits (ICs)and methods of fabrication thereof, and more specifically to asemiconductor IC with minimized dimensions for contact openings andmethods for the fabrication of thereof.

[0003] 2. Related Art

[0004] The ability to scale the size of semiconductor device geometriesdownward is key to meeting the demands for integrated circuits havingincreased functionality and performance while maintaining lowfabrication costs. The industry's ability to meet this demand to datehas very much been due to improvements in the optical resolution ofphotolithography equipment and associated processes. However, the fullimpact of these improvements is often not realized, as process bufferingregions are needed to account for registration and other processtolerances. This is particularly true for contact openings.

[0005] For example, in the manner of the prior art, FIG. 1A depicts aplan view of a first contact opening 40 formed overlying a firstconductive trace 30. Typically, both first trace 30 and first contact 40are formed having a minimum design dimension. Thus, first trace 30 has awidth 50 and first contact 40 a width 52 that are essentially equal.However, to ensure that first contact 40 overlies only first trace 30,contact 40 is positioned within a contact region 34, an expanded regionof trace 30, that has a dimension 54, larger than widths 50 and 52. Thesize difference between width 54 and width 50 is the amount of processbuffering required to form first contact 40 entirely overlyingconductive trace 30. Therefore despite less than perfect alignment offirst opening 40 to first trace 30, as depicted, contact opening 40 isfully within contact region 34. Where a second conductive trace 32 doesnot provide any process buffering region, that is no region analogous toexpanded region 34, the less than perfect alignment of a second contact42 to second trace 32 results in second contact 42 being positionedhaving a portion of second contact 42 off second trace 34, as depicted.As known, such mis-positioning can result in both yield and reliabilityproblems. Thus to avoid these problems, prior art processing providesprocess buffering regions.

[0006] Expanded process buffering regions, such as contact region 34,are not the only forms of process buffering regions employed in theprior art. Turning now to FIG. 1B, a plan view of a metal on silicon(MOS) transistor 90 is shown. An active area 80 has source and drain(S/D) regions 62 formed therein. A gate electrode 70 is disposedadjacent to and between S/D regions 62 and overlying a channel region(not shown) in active area 80 bordered by S/D regions 62. Electricalcontact to gate electrode 70 is made within a process buffering region74 extending outward from area 80, as depicted. As known, an extendedprocess buffering region, such as region 74, is often employed in priorart MOS transistors for providing electrical contact to gate electrode70. Use of an expanded buffering region, such as region 34 of FIG. 1A,is problematic as such an expanded region increases gate length. Asknown, an increased gate length will result in a change in theelectrical characteristics of transistor 90 from that of a transistorhaving the nominal gate length. On the other hand, failure to use anyprocess buffering region, as shown for second contact 42 in FIG. 1A, canresult in lowered yield and reliability due to electrical shorting ofgate 70 to S/D regions 60. Therefore the-prior art process and MOStransistors formed thereby, require that an extension of gate 70 beemployed to form process buffering region 74 and that gate contact 72 isdisposed within extended region 74. Hence it can be seen that contactsformed in the manner of the prior art require either expanded processbuffering regions or extended process buffering regions. And that thesebuffering regions require substrate surface area in excess of thatrequired by the functional structures themselves, for example trace 32and contact 42 of FIG. 1A. Thus, processing in the manner of the priorart does not allow for the full realization of the benefits thatdownward scaling of device structures can provide.

[0007] Thus it would be advantageous to have IC structures and devicesthat realize the full benefit of scaling the size of such structures anddevices downward, and the methods of manufacture thereof. It would alsobe advantageous to have methods for forming such fully realized sizescaled devices and structures that do not require additionalphotomasking processes. In addition it would be advantageous for suchmethods of manufacture to be broadly applicable, thus providing for themanufacture of both MOS and Bipolar devices as well as any combinationof such devices thereof that fully realize such size scaling. Finally,it would be advantageous to manufacture such fully realized size scaleddevices in a cost effective manner and where devices so manufacturedhave yield and reliability at least equal to that of the prior art.

SUMMARY

[0008] In accordance with the present invention, methods for formingminimized area contact structures, and the structures and IC's formedthereby, are provided. In some embodiments of the present invention, MOSintegrated circuits and circuit elements are formed. In some embodimentsof the present invention, bipolar integrated circuits and circuitelements are formed and in some embodiments, both MOS and bipolarcircuit elements and circuit elements are formed.

[0009] In accordance with the present invention some embodiments employa non-conductive material to form process buffering regions adjacentconductive traces. In some embodiments the non-conductive materialemployed is a dielectric material such as silicon oxide, silicon nitrideor a combination of silicon oxide and silicon nitride. In someembodiments both silicon oxide and silicon nitride materials areemployed. In some embodiments of the present invention the dielectricmaterial is formed as a layer overlying a semiconductor substrate andselectively etched to form process buffering regions or processbuffering spacers adjacent sidewalls of the conductive traces formed onthe substrate. In some embodiments process buffering spacers are formedusing more than one layer of dielectric material.

[0010] Embodiments in accordance with the present invention typicallyemploy a dielectric layer disposed over the process buffering regions.In some embodiments, the material of the process buffering regions isselectively etchable with respect to the dielectric layer. In someembodiments the dielectric layer is formed of more than one layer ofdielectric material, each layer being selectively etchable with respectto an underlying layer. In some embodiments of the present inventioncontact holes or vias are formed by etching portions of the dielectriclayer left exposed after deposition and patterning of a photomaskinglayer to define such portions. In embodiments where a conductive traceis a gate electrode, process buffering regions formed in accordance withthe present invention allow direct contact to be made to the gateelectrode, if desired. Finally, in some embodiments, the processbuffering regions formed, prevent exposure of sidewalls of theconductive traces. In this manner, embodiments in accordance with thepresent invention avoid the need for formation of either expanded orextended process buffering regions, thus enabling minimized areacontacts.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention may be better understood, and its numerousobjects, features, and advantages made apparent to those skilled in theart by referencing the accompanying drawings. For ease of understandingand simplicity, where elements are common between illustrations, commonnumbering of those elements is employed between illustrations.

[0012]FIGS. 1A and 1B are plan views of conductive traces and contactregions formed in the manner of the prior art;

[0013] FIGS. 2A-2E are cross-sectional representations of stages in theformation of contact regions on conductive traces in accordance with anembodiment of the present invention; and

[0014] FIGS. 3A-3B are a plan and cross-sectional representation,respectively, of contact regions on a gate electrode in accordance withanother embodiment of the present invention.

DETAILED DESCRIPTION

[0015] As embodiments of the present invention are described withreference to the drawings, various modifications or adaptations of thespecific methods and or structures may become apparent to those skilledin the art. All such modifications, adaptations or variations that relyupon the teachings of the present invention, and through which theseteachings have advanced the art, are considered to be within the spiritand scope of the present invention. For example, in some embodiments ofthe present invention, process buffering spacers are formed afterremoval of sidewall spacers used for, among other things, formation ofsilicide regions.

[0016] FIGS. 2A-2E depict a series of stages in the fabrication of anembodiment in accordance with the present invention. As shown, in eachof FIGS. 2D and 2E, a first portion and a second portion of theembodiment are depicted. The first portion, on the left, illustrates anembodiment of the invention having a slight mis-alignment, as was seenwith respect to the prior art conductive trace 30 and contact 40 in FIG.1A. The second portion, on the right, illustrates an embodiment of theinvention having less than perfect alignment as was seen with respect tothe prior art conductive trace 32 and contact 42, also in FIG. 1A.

[0017] Turning to FIG. 2A, a semiconductor substrate or wafer 100 isshown having a conductive layer 200 disposed thereon. While wafer 100 isdepicted as having a minimum of complexity, other types of substrates orwafers may be advantageously employed. For example, substrate 100 can bean N-type or P-type substrate, or can be an N-type or P-type substrateencompassing N and/or P-type well regions (not shown) and/or anepitaxial layer (not shown). Alternatively, wafer 100 can encompass asilicon on insulator (SOI) structure, or any other appropriatesemiconductor substrate material or structure. In addition, in someembodiments in accordance with the present invention, substrate 100encompasses a dielectric layer (not shown) formed on an upper surfaceand disposed underlying layer 200. Two masking portions 300 and 320 aredepicted overlying predetermined portions of conductive layer 200.Typically, masking portions 300 and 320 are a photoresist materialformed by well known photolithographic processes, although otherappropriate materials can be employed in addition to or in place ofphotoresist.

[0018] Conductive layer 200 is any of the commonly employed conductivematerials or combination of such materials used to form conductive pathsor traces for IC's. For example, in some embodiments layer 200 canencompass aluminum, copper or an alloy of aluminum and/or copper. Layer200 can also encompass more than one layer of conductive material, forexample, a conductive barrier layer such as tungsten or a tungsten alloyoverlaid with an aluminum layer. In some embodiments layer 200 can alsoencompass a polysilicon material, an amorphous silicon material or anycombination of amorphous and polysilicon doped with an N or P-typedopant. In some embodiments of the present invention, where layer 200 isa polysilicon layer formed adjacent substrate 100, layer 200 is a firstconductive layer of an IC having multiple conductive layers. In someembodiments, where layer 200 is an aluminum alloy layer, layer 200 isone conductive metal layer of an IC having a multilayer metal structure.In some embodiments, layer 200 is employed to form a silicon or metalgate electrode (not shown). Therefore it will be understood that therepresentation of layer 200 in FIG. 2B and the structures of FIGS. 2A-2Eare all depicted in their simplest form for illustrative purposes only,and that embodiments of the present invention have a wide range ofspecific application.

[0019] Referring to FIG. 2B, conductive layer 200 (FIG. 2A) is etched toform conductive paths or traces 210 and 220, and masking portions 300and 320 (FIG. 2A) is subsequently removed. After removal of portions 300and 320, an essentially conformal layer 400 of a dielectric material isformed overlying substrate 100 and conductive traces 210 and 220. Insome embodiments of the present invention, layer 400 encompasses siliconoxide, silicon nitride or any combination of silicon oxide and siliconnitride, although other appropriate materials can be employed.

[0020] Turning now to FIG. 2C, the structure of FIG. 2B is shownsubsequent to forming process buffering areas or spacers 410. Asdepicted, process buffering spacers 410 are formed adjacent sidewalls ofconductive traces 210 and 220, and have a predetermined width 415. Itwill be understood that width 415 defines the amount of processbuffering that an embodiment in accordance with the present inventionprovides. Thus, with knowledge of the process capabilities of thevarious processes for which such process buffering is needed, width 415is determined to be the sum of the buffering required for each of thevarious processes. For example, where a photolithography processrequires 0.1 micron (μm) of buffering and is followed by an etch processalso requiring 0.1 μm of process buffering, width 415 is the sum ofthese two processes, 0.2 μm. It will be understood that while themagnitude of width 415 needed by a specific application is determined bythe amount of process buffering required, width 415 is set by thethickness of layer 400 (FIG. 2B) as formed. Thus, for a 0.2 μm width415, layer 400 is formed having a thickness of at least 0.2 μm. Wheremore or less process buffering is required, layer 400 is formed with agreater or lesser thickness, respectively. Thus the thickness of layer400, as deposited, will vary in accordance with the nature of thespecific application for which an embodiment of the present invention isemployed.

[0021] Typically, process buffering areas 410 are formed using ananisotropic etch process appropriate for the material from which layer400 (FIG. 2B) is formed. As one having ordinary skill in the art willknow, the specific etch process selected will be selective to thematerial employed for conductive traces 210 and 220 as well as anyunderlying dielectric layer (not shown). In this manner, spacers 410 areformed adjacent sidewalls of each trace 210 and 220 while an uppersurface 215 and 225 of each trace, respectively, is exposed. Forexample, where conductive traces 210 and 220 are doped polysilicontraces overlying a substrate 100 having an upper surface formed of asilicon oxide dielectric layer (not shown) and layer 400 (FIG. 2B) isselected to be a silicon nitride material, process buffering spacers 410are formed employing an etch process that preferentially etches siliconnitride. For example, a reactive ion etch (RIE) process employing amixture of CHF₃/O₂ and C₂HF₅ at an appropriate power and pressure hasbeen found to be effective, although other etch process can also beemployed. It will be understood that the etch process of this embodimentof the present invention is only provided for illustrative purposes andother etch processes can be employed where appropriate.

[0022] Turning now to FIG. 2D, as previously mentioned, a first andsecond portion of the embodiment of FIG. 2C, in accordance with thepresent invention, is shown. In each portion, a dielectric layer 500 isformed overlying each conductive trace 210 and 220, respectively, andunderlying substrate 100. In some embodiments, one of the commonly knownplanarization processes is employed to planarize layer 500, as isdepicted. For example, in some embodiments layer 500 is planarized usinga chemical mechanical planarization (CMP) process, while in someembodiments a sacrificial layer/etch-back process is employed.

[0023] A masking layer 600 is disposed on layer 500 and a first contactarea 610 is formed in layer 600 to expose a portion of layer 500overlying a portion of conductive trace 210 and a portion of one processbuffering area 410. Thus contact area 610 is shown aligned to trace 210in a manner analogous to the alignment of contact 40 to trace 30depicted in FIG. 1A. In the second portion of the embodiment of FIG. 2D,a second contact area 620 is formed in layer 600 to expose anotherportion of layer 500 overlying a portion of conductive trace 220, aportion of one process buffering area 410 and extending to expose someof layer 500 beyond that process buffering area 410. The alignment ofcontact area 620 is in a manner analogous to the alignment of contact 42to trace 32 depicted in FIG. 1B. It will be understood that thealignment of areas 610 and 620 are shown in the manner of the alignmentof contact 40 and 42 for illustrative purposes only. Thus thesedepictions of FIG. 2D serve to highlight, as will be discussed, theadvantages of embodiments of the present invention as compared to thepreviously illustrated prior art structures.

[0024]FIG. 2E is a cross-sectional view of the embodiments of FIG. 2Dsubsequent to etching layer 500 to form a first contact 510, a secondcontact 520 and removal of masking layer 600. As depicted, first contact510 exposes surface 215 of conductive trace 210. In addition, a portionof process buffering area 410 adjacent trace 210 is exposed. Thus theslight mis-alignment of contact area 610 (FIG. 2D) is accommodated byprocess buffering spacer 410 and no expanded contact region as seen inFIG. 1A is required. Second contact 520 exposes surface 225 ofconductive trace 220, a portion of buffering spacer 410 and an edge 430of buffering spacer 410. Thus, it will be understood that processbuffering spacer 410 advantageously protects edge 230 of conductivetrace 220 from being exposed, despite the misalignment of contact 520.

[0025] As known for the prior art structure of FIG. 1B, where contact 42is formed over an aluminum (Al) trace 32, any exposed edge of Al trace32 can lead to the formation aluminum fluoride (AlF₃) and/or “volcano”defects where a tungsten (W) plug (not shown) is formed to subsequentlyfill contact 42. For embodiments of the present invention, edge 230 isnot exposed, but rather protected by buffering spacer 410. Thusembodiments in accordance with the present invention advantageouslyprovide protection against such yield and reliability as AlF₃ and“volcano” defects.

[0026] In addition, where trace 220 is a polysilicon material, often ametal silicide is formed at surface 225 to enhance electrical couplingby lowering the resistance of the surface. As known, where edge 230 isexposed during a silicide process, metal silicide (not shown) canundesirably form at edge 230 providing for unplanned and thereforeundesirable electrical coupling to other closely spaced conductiveregions (not shown). Therefore, embodiments in accordance with thepresent invention advantageously provide protection against suchundesirable couplings.

[0027] It will also be understood, that the advantages of embodiments ofthe present invention, as described herein, are provided without use ofexpanded contact areas or extended contact areas as described withregard to the prior art (See FIGS. 1A and 1B). Therefore, embodiments inaccordance with the present invention do not require the additional arearequired by these prior art contact areas, and minimized contact areasare provided.

[0028] Turning now to FIG. 3A, a plan view of an MOS transistor 900formed in accordance with an embodiment of the present invention isdepicted. An active area 800 is defined by an isolation region 700 andhas S/D regions 820 formed therein. The nature of embodiments of thepresent invention make them applicable to any type of MOS transistor900. Thus the benefits and advantages of the present invention areequally applicable to an NPN or a PNP transistor 900. In addition, thebenefits and advantages of the present invention are equally applicableto MOS transistors formed having silicon gates or metal gates. Inaddition, as the characteristics of S/D regions 820, isolation region700 and other transistor structures depicted in FIGS. 3A and 3B are wellknown and additionally encompass well known and commonly practicedmethods, for simplicity and ease of understanding, descriptions of thesecharacteristics and methods will be omitted. A gate electrode 840 isdisposed adjacent to and between S/D regions 820 and overlying a channelregion (not shown) defined by S/D regions 820 in active area 800. Whilegate electrode 840 is typically formed from a polysilicon material,other appropriate materials can be used. For example, gate electrode 840can be formed using amorphous silicon which is converted in-situ topolysilicon in a manner known to one of ordinary skill in the art. Inaddition, in some embodiments in accordance with the present invention,gate electrode 840 is a metal such as tungsten (W), molybdenum (Mo) ortantalum (Ta). For example, in some embodiments a W gate electrode 840is advantageously used. Alternatively, in some embodiments it isadvantageous to employ a Mo or Ta gate electrode 840. Gate processbuffering areas 810 are depicted adjacent edges of gate electrode 840.Buffering areas 810 are formed of any of the materials, and in themanner described with respect to FIGS. 2B and 2C. S/D contacts 920 areformed overlying and within S/D regions 820. As known, gate contact 940and S/D contacts 920 are formed in a dielectric layer not visible in aplan view. It will be understood, that as transistor 900 is formed inaccordance with embodiments of the present invention, no extendedcontact area as seen in FIG. 1B is needed.

[0029]FIG. 3B is a cross-sectional view of transistor 900 of FIG. 3Ataken through section line BB. Thus active area 800 is shown defined byisolation region 700. Gate electrode 840 with adjacent gate bufferingareas 810 is shown overlying a gate dielectric 730 and channel region830 which in turn is seen to be adjacent S/D regions 820. In embodimentsof the present invention employing a silicon gate electrode 840, gatedielectric 730 is typically formed of a silicon oxide material, althoughother appropriate materials can be used. In embodiments where gateelectrode 840 is a metal material, for example tungsten (W), a Ta₂O₅gate dielectric layer 730 can be advantageously used. In someembodiments employing a Mo or Ta gate electrode 840 a silicon oxide gatedielectric layer 730 having an intervening barrier layer such astitanium/titanium nitride (not shown) is employed. The cross-sectionalview of FIG. 3A illustrates the formation of gate contact 940 and S/Dcontacts 920 in dielectric layer 720 as previously mentioned. It will beunderstood that the In addition, process buffering areas 810 are formedof materials and by the methods previously described for embodiments ofbuffering areas 410 with regard to FIGS. 2B and 2C. Therefore, thesematerials and methods are understood to be applicable to the formationof gate process buffering areas or spacers 810 as well.

[0030] In a manner analogous to the first portion of FIG. 2E, it is seenthat gate contact 940 is formed exposing surface 845 of gate electrode840. In embodiments of the present invention where gate electrode 840encompasses a silicon material, it is advantageous to form a metalsilicide contact region (not shown) at surface 845. As known, such metalsilicide regions serve to lower the contact resistance to gate electrode840. While in accordance with the present invention, any of the wellknown processes for forming such metal silicide regions can be employed,it is a particular benefit of the present invention that processbuffering regions 810 limit any metal silicide formation to surface 845.Thus gate electrode edge 842 is free of such metal silicide formation.In embodiments of the present invention where gate electrode 840encompasses a metal material, no metal silicide region is formed atsurface 845.

[0031] It will also be understood, that the advantages of embodiments ofthe present invention previously described with respect to FIG. 2E arealso provided by the embodiment of FIGS. 3A and 3B. Thus it will berealized that embodiments of the present invention have been describedthat provide for semiconductor integrated circuits, and methods thereof,that employ minimized area contacts. In addition, it will be realizedthat embodiments in accordance with the present invention do not requirethe additional area required by these prior art expanded or extendedcontact areas. Additionally, it will realized that the embodiments ofthe present invention described herein do not require anyphotolithographic processing for their benefits to be realized. It willalso be realized that embodiments of the present invention are broadlyapplicable to a wide range of semiconductor structures and devices. Andthat while only an MOS transistor has been specifically described, thatthe process buffering provided by these embodiments is applicable to MOSICs as well as bipolar ICs and ICs that combine MOS and bipolar devicestructures. For example, process buffering areas analogous to thosepreviously described herein can be utilized to form minimized areacontacts to bipolar base, collector or emitter regions. Thus, the methodof formation and structure of process buffering areas for thepolysilicon emitter region of a bipolar transistor are readilydetermined from the descriptions herein. It will also be realized thatembodiments of the present invention provide protection to sidewalls ofconductive traces, for example gate electrodes. Thus where metalsilicide regions are formed, this protection serves to prevent formationof metal silicide on such sidewalls. Finally, it will be realized thatembodiments of the present invention are cost effect structures thatoffer yield and reliability enhancement.

I claim:
 1. A method of forming a semiconductor integrated circuitdevice, comprising the steps of: providing a semiconductor substrate;forming a conductive trace overlying said semiconductor substrate,wherein said conductive trace has essentially parallel sidewalls;forming a process buffering area adjacent each sidewall, said processbuffering areas having a predetermined width; forming a layer ofinsulating material overlying said conductive trace and processbuffering areas; and forming a contact opening in said layer ofinsulating material, wherein said contact opening is positionedoverlying a portion of said conductive trace and at least one of saidprocess buffering areas.
 2. The method of claim 1 wherein forming aprocess buffering area having a predetermined width comprises forming aprocess buffering area having a width equal to the sum of the processbuffering requirements of relevant process steps.
 3. The method of claim2 wherein forming a process buffering area comprises the steps of:forming a layer of dielectric material overlying said substrate and saidconductive traces; and anisotropically etching said layer of dielectricmaterial to expose an upper surface of said conductive trace.
 4. Themethod of claim 3 wherein forming a layer of dielectric materialcomprises forming said layer of dielectric material of a dielectricmaterial comprising silicon oxide and/or silicon nitride.
 5. The methodof claim 3 wherein forming a layer of dielectric material comprisesforming a layer comprising silicon oxide disposed overlying saidconductive trace and forming a layer comprising silicon nitride disposedoverlying said layer comprising silicon oxide.
 6. The method of claim 1wherein forming a conductive trace comprises the steps of: depositing alayer of a conductive material disposed overlying a semiconductor wafer;and anisotropically etching said layer of conductive material whereinsaid conductive trace is formed having essentially parallel sidewalls.7. The method of claim 6 wherein depositing a layer of a conductivematerial comprises depositing a conductive material selected from thegroup consisting of aluminum, copper, tungsten, tantalum, molybdenum andcombinations thereof
 8. The method of claim 6 wherein depositing a layerof a conductive material comprises depositing a conductive materialcomprising polysilicon and/or amorphous silicon.
 9. The method of claim6 wherein depositing a layer of a conductive material comprises thesteps of: depositing a first layer of conductive material; patterningand etching said first layer of conductive material to form at least onefirst conductive trace; depositing a layer of insulating material toform an interlayer dielectric disposed overlying said first conductivetrace; depositing a second layer of conductive material disposedoverlying said interlayer dielectric; and patterning and etching saidsecond layer of conductive material to form at least one secondconductive trace.
 10. A semiconductor device comprising: a semiconductorwafer; a conductive path overlying said semiconductor wafer, whereinsaid path comprises a width defined by essentially parallel, opposingsidewalls; a dielectric process buffering spacer adjacent each of saidopposing sidewalls; an insulating layer overlying said wafer, saidconductive path and said process buffering spacers; and a contactopening having a dimension parallel to said width, wherein said contactopening is disposed overlying a portion of said conductive path and aportion of at least one process buffering spacer, and wherein saiddimension is essentially equal to said width.
 11. The semiconductordevice of claim 10 wherein said width is equal to the sum of the processbuffering requirements of relevant process steps.
 12. The semiconductordevice of claim 10 wherein said process buffering spacer comprisessilicon oxide and/or silicon nitride.
 13. The semiconductor device ofclaim 10 wherein said process buffering spacer comprises a layercomprising silicon oxide disposed overlying a layer comprising siliconnitride.
 14. The semiconductor device of claim 10 wherein saidconductive path comprises a conductive material selected from the groupconsisting of aluminum, copper, tungsten, tantalum, molybdenum,polysilicon, amorphous silicon and combinations thereof.
 15. Thesemiconductor device of claim 10 wherein said conductive path is a gateelectrode.
 16. The semiconductor device of claim 15 wherein said gateelectrode comprises a material selected from the group consisting oftungsten, tantalum, molybdenum, polysilicon, amorphous silicon andcombinations thereof.